OpenWrt/LEDE Project

  • Status Unconfirmed
  • Percent Complete
    0%
  • Task Type Bug Report
  • Category Kernel
  • Assigned To No-one
  • Operating System All
  • Severity Low
  • Priority Very Low
  • Reported Version Trunk
  • Due in Version Undecided
  • Due Date Undecided
  • Private
Attached to Project: OpenWrt/LEDE Project
Opened by Aleksey Tregubov - 23.01.2021

FS#3591 - mt7621 trunk initialize properly only one pcie wifi card

As addition to FS#3381 – current trunk initialize properly only one minipcie wifi card:

[ 1.344484] pci 0000:02:00.0: [168c:ff1c] type 00 class 0×020000 [ 1.350550] pci 0000:02:00.0: reg 0×10: [mem 0×00000000-0x0000ffff 64bit]
[ 1.357475] pci 0000:02:00.0: supports D1
[ 1.361487] pci 0000:02:00.0: PME# supported from D0 D1 D3hot
[ 1.368492] pci 0000:00:01.0: PCI bridge to [bus 02-ff]
[ 1.373756] pci 0000:00:01.0: bridge window [io 0×0000-0x0fff]
[ 1.379843] pci 0000:00:01.0: bridge window [mem 0×60200000-0x602fffff]
[ 1.386624] pci 0000:00:01.0: bridge window [mem 0×60300000-0x603fffff pref]
[ 1.393842] pci_bus 0000:02: busn_res: [bus 02-ff] end is updated to 02
[ 1.400681] pci 0000:03:00.0: [168c:002e] type 00 class 0×028000 [ 1.406748] pci 0000:03:00.0: reg 0×10: [mem 0×00000000-0x0000ffff 64bit]
[ 1.413660] pci 0000:03:00.0: supports D1
[ 1.417671] pci 0000:03:00.0: PME# supported from D0 D1 D3hot
[ 1.424673] pci 0000:00:02.0: PCI bridge to [bus 03-ff]
[ 1.429917] pci 0000:00:02.0: bridge window [io 0×0000-0x0fff]
[ 1.436004] pci 0000:00:02.0: bridge window [mem 0×60400000-0x604fffff]
[ 1.442785] pci 0000:00:02.0: bridge window [mem 0×60500000-0x605fffff pref]
[ 1.450010] pci_bus 0000:03: busn_res: [bus 03-ff] end is updated to 03


Aleksey Tregubov commented on 23.01.2021 23:01

Found some solution. After applying this patch trunk works fine:

--- pci-mt7621.c.org	2021-01-24 01:56:39.085392065 +0300
+++ pci-mt7621.c	2021-01-24 01:55:53.735426130 +0300
@@ -503,7 +503,12 @@
 
 	rt_sysc_m32(PERST_MODE_MASK, PERST_MODE_GPIO, MT7621_GPIO_MODE);
 
+    mdelay(250);
+
 	mt7621_pcie_reset_assert(pcie);
+
+    mdelay(250);
+
 	mt7621_pcie_reset_rc_deassert(pcie);
 
 	list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
@@ -521,6 +526,8 @@
 		}
 	}
 
+    mdelay(250);
+
 	mt7621_pcie_reset_ep_deassert(pcie);
 
 	tmp = NULL;

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