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[ 0.198279] rk_gmac-dwmac ff540000.ethernet: phy regulator is not available yet, deferred probing
[ 0.200603] dwc3 ff600000.dwc3: Failed to get clk 'ref': -2
[ 35.824776] mmc_host mmc0: Bus speed (slot 0) = 400000Hz (slot req 400000Hz, actual 400000HZ div = 0)
[ 35.878229] mmc_host mmc0: Bus speed (slot 0) = 150000000Hz (slot req 150000000Hz, actual 150000000HZ div = 0)
[ 36.037807] dwmmc_rockchip ff500000.dwmmc: Successfully tuned phase to 190
[ 44.388814] mmc_host mmc0: Bus speed (slot 0) = 400000Hz (slot req 400000Hz, actual 400000HZ div = 0)
[ 44.548904] mmc_host mmc0: Bus speed (slot 0) = 150000000Hz (slot req 150000000Hz, actual 150000000HZ div = 0)
[ 44.590737] dwmmc_rockchip ff500000.dwmmc: All phases work, using default phase 0.
[ 45.361969] mmc_host mmc0: Bus speed (slot 0) = 400000Hz (slot req 400000Hz, actual 400000HZ div = 0)
[ 45.520553] mmc_host mmc0: Bus speed (slot 0) = 150000000Hz (slot req 150000000Hz, actual 150000000HZ div = 0)
[ 45.558426] dwmmc_rockchip ff500000.dwmmc: All phases work, using default phase 0.
[ 55.906843] mmc_host mmc0: Bus speed (slot 0) = 400000Hz (slot req 400000Hz, actual 400000HZ div = 0)
[ 56.087807] mmc_host mmc0: Bus speed (slot 0) = 150000000Hz (slot req 150000000Hz, actual 150000000HZ div = 0)
[ 56.125748] dwmmc_rockchip ff500000.dwmmc: All phases work, using default phase 0.
The text was updated successfully, but these errors were encountered:
peterwillcn:
[ 0.198279] rk_gmac-dwmac ff540000.ethernet: phy regulator is not available yet, deferred probing
[ 0.200603] dwc3 ff600000.dwc3: Failed to get clk 'ref': -2
[ 35.824776] mmc_host mmc0: Bus speed (slot 0) = 400000Hz (slot req 400000Hz, actual 400000HZ div = 0)
[ 35.878229] mmc_host mmc0: Bus speed (slot 0) = 150000000Hz (slot req 150000000Hz, actual 150000000HZ div = 0)
[ 36.037807] dwmmc_rockchip ff500000.dwmmc: Successfully tuned phase to 190
[ 44.388814] mmc_host mmc0: Bus speed (slot 0) = 400000Hz (slot req 400000Hz, actual 400000HZ div = 0)
[ 44.548904] mmc_host mmc0: Bus speed (slot 0) = 150000000Hz (slot req 150000000Hz, actual 150000000HZ div = 0)
[ 44.590737] dwmmc_rockchip ff500000.dwmmc: All phases work, using default phase 0.
[ 45.361969] mmc_host mmc0: Bus speed (slot 0) = 400000Hz (slot req 400000Hz, actual 400000HZ div = 0)
[ 45.520553] mmc_host mmc0: Bus speed (slot 0) = 150000000Hz (slot req 150000000Hz, actual 150000000HZ div = 0)
[ 45.558426] dwmmc_rockchip ff500000.dwmmc: All phases work, using default phase 0.
[ 55.906843] mmc_host mmc0: Bus speed (slot 0) = 400000Hz (slot req 400000Hz, actual 400000HZ div = 0)
[ 56.087807] mmc_host mmc0: Bus speed (slot 0) = 150000000Hz (slot req 150000000Hz, actual 150000000HZ div = 0)
[ 56.125748] dwmmc_rockchip ff500000.dwmmc: All phases work, using default phase 0.
The text was updated successfully, but these errors were encountered: